1. Field of the Invention
The present invention relates generally to memory cell structures employed within semiconductor integrated circuit fabrications. More particularly, the present invention relates to capacitor under bitline (CUB) memory cell structures employed within semiconductor integrated circuit fabrications.
2. Description of the Related Art
Semiconductor integrated circuit fabrications are formed from semiconductor substrates within and upon which are formed semiconductor devices, and over which are formed patterned conductor layers which are separated by dielectric layers.
Common in the art of semiconductor integrated circuit fabrication, and in particular in the art of semiconductor memory fabrication, is the use and the fabrication of memory cell structures, and in particular dynamic random access memory (DRAM) cell structures. Dynamic random access memory (DRAM) cell structures typically comprises a field effect transistor (FET) device formed within and upon a semiconductor substrate, where one of a pair of source/drain regions within the field effect transistor (FET) device has formed thereover and in electrical communication therewith a storage capacitor. Within a dynamic random access memory (DRAM) cell structure, a gate electrode of the field effect transistor (FET) device serves as a wordline which provides a switching function for charge introduction and retrieval from the storage capacitor, while the other of the pair of source/drain regions within the field effect transistor (FET) device serves as a contact for a bitline conductor stud which introduces or retrieves charge with respect from the storage capacitor.
While the dynamic random access memory (DRAM) cell structure has clearly become ubiquitous in the art of semiconductor memory fabrication, and is thus essential in the art of semiconductor integrated circuit fabrication, the dynamic random access memory (DRAM) cell structure is nonetheless not entirely without problems in the art of semiconductor memory fabrication.
In that regard, as semiconductor integration levels have increased and semiconductor device and patterned conductor layer dimensions have decreased, it has become increasingly difficult in the art of semiconductor integrated circuit fabrication, and in particular in the art of semiconductor memory fabrication, to fabricate semiconductor integrated circuit fabrications with optimal and enhanced performance. Similarly, a common impediment to optimal and enhanced performance within advanced semiconductor integrated circuit fabrications is parasitic capacitive coupling losses between various structures within semiconductor integrated circuit fabrications.
It is thus desirable in the art of semiconductor integrated circuit fabrication, and in particular in the art of semiconductor memory fabrication, to provide methods and materials through which there may be formed, with enhanced performance, semiconductor integrated circuit fabrications.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed in the art of semiconductor integrated circuit microelectronic fabrication for forming, with desirable properties, semiconductor integrated circuit fabrications.
Included among the methods, but not limited among the methods, are methods disclosed within Chi, in U.S. Pat. No. 6,174,767 (a method for forming a capacitor and bitline structure within a dynamic random access memory (DRAM) cell structure for use within a semiconductor memory fabrication, with attenuated bitline to bitline capacitance within the capacitor and bitline structure, by forming a pair of bitline structures within the capacitor and bitline structure at an equivalent topographic level with a capacitor within the capacitor and bitline structure).
Desirable in the art of semiconductor integrated circuit fabrication, and in particular in the art of semiconductor memory fabrication, are additional methods and materials which may be employed for forming, with enhanced performance, semiconductor integrated circuit fabrications.
It is towards the foregoing object that the present invention is directed.
A first object of the invention is to provide a semiconductor integrated circuit fabrication and a method for fabricating the semiconductor integrated circuit fabrication.
A second object of the present invention is to provide a semiconductor integrated circuit fabrication and a method for fabricating the semiconductor integrated circuit fabrication in accord with the first object of the present invention, wherein the semiconductor integrated circuit fabrication is formed with enhanced performance.
A third object of the present invention is to provide a semiconductor integrated circuit fabrication and a method for fabricating the semiconductor integrated circuit fabrication in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention: (1) a method for fabricating a memory cell structure; and (2) a memory cell structure which results from the method for fabricating the memory cell structure.
To practice the method of the present invention, there is first provided a semiconductor substrate. There is then formed within and upon the semiconductor substrate a field effect transistor (FET) device comprising a gate dielectric layer formed upon the semiconductor substrate, a gate electrode formed upon the gate dielectric layer and a pair of source/drain regions formed into the semiconductor substrate and separated by the gate electrode. There is then formed over the field effect transistor (FET) device and in electrical communication with one of the pair of source/drain regions within the field effect transistor (FET) device a capacitor structure having a sidewall. Finally, there is then formed over the field effect transistor (FET) device and in electrical communication with the other of the pair of source/drain regions within the field effect transistor (FET) device a bitline stud layer adjacent to and extending above the sidewall of the capacitor structure. Within the present invention, the bitline stud layer is separated from the sidewall of the capacitor structure at least in part by an air gap void.
The method for fabricating the memory cell structure in accord with the present invention contemplates a memory cell structure fabricated in accord with the method for fabricating the memory cell structure in accord with the present invention.
The present invention provides a semiconductor integrated circuit fabrication and a method for fabricating the semiconductor integrated circuit fabrication, wherein the semiconductor integrated circuit fabrication is formed with enhanced performance.
The present invention realizes the foregoing object by employing when forming a memory cell structure for use within a semiconductor integrated circuit fabrication an air gap void interposed, at least in part, between: (1) a sidewall of a capacitor structure in electrical communication with one of a pair of source/drain regions within a field effect transistor (FET) device within the memory cell structure; and (2) a bitline stud layer in electrical communication with the other of the pair of source/drain regions within the field effect transistor (FET) device, where the bitline stud layer is adjacent to and extends above the sidewall of the capacitor structure. Within the present invention, the air gap void provides for attenuated parasitic capacitance between the capacitor structure and the bitline stud layer.
The method of the present invention is readily commercially implemented.
The present invention employs methods and materials as are generally known in the art of semiconductor integrated circuit fabrication, but employed within the context of a specific process ordering and specific materials limitations to provide a memory cell structure in accord with the present invention. Since it is thus at least in part a specific process ordering and specific materials limitations which provide at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.